Single-instruction, multiple-data (SIMD) operations are an efficient computational schema commonly applied to digital signal processing algorithms. The Intel MMX and SSE (Streaming SIMD Extensions) instructions give programmers a means to operate on multiple data elements and deliver substantially increased performance for applications typically delegated to expensive digital signal processors (DSP).
Download the following whitepaper to see what level of performance gains are possible when using SIMD instructions and the IPP library on the INtime RTOS:
Or read the whitepaper on-line to see how dedicating a processor core to an IPP-enabled INtime application can eliminate the need for an expensive DSP in your embedded system.
The Intel Integrated Performance Primitives (the IPP library) deliver a rich set of options from which to choose and optimize your use of the Intel MMX and SSE instruction sets, automatically adjusting to support the feature set of the specific processor on which your application is run. Using the library simplifies the integration of DSP functionality into your applications, so you can focus your time and effort on building the value-add functionality that will differentiate your product in the market.
The Intel IPP library includes functions for algorithms in the following categories:
Sophisticated primitives designed for the construction of audio, video and speech codecs such as MP3 (MPEG-1 Audio, Layer 3), MPEG-4, H.264, VC-1,H.263, JPEG, JPEG2000, G.729, and computer vision are also included.
TenAsys is not an authorized reseller for the Intel IPP library. Please visit the Intel IPP page or contact your authorized Intel reseller for pricing and availability of the Intel IPP library. You need the standard Intel® Integrated Performance Primitives for Windows product in order to integrate the IPP library with INtime real-time applications.
Microsoft Visual Studio is all that is required to create IPP applications for the INtime RTOS. All the standard INtime wizards and debug tools are available for development of your application.
INtime applications are limited to use of the IPP static linkage models. Run-time dispatch (automatic detection of the underling CPU) is supported by the static linkage model, insuring that optimum performance of the IPP library is always acheived, regardless of the specific processor platform.
Intel Pentium 4, Xeon and Pentium M processors include support for MMX through SSE2 technology. Processors based on Intel Core and Intel Atom support the MMX, SSE, SSE2, SSE3, and SSSE3 instruction sets. Those based on the Intel Core 2 Duo also support the SSE4.1 instruction set. And processors based on the Intel Core i7 architecture support the SSE4.2 instruction set.